1. Field of the Invention:
The present invention relates to a semiconductor integrated circuit device using MOS transistors formed in silicon layers on a buried oxide film (SOI: Silicon On Insulator).
2. Description of the Prior Art:
Each of CMOS devices (SOI/CMOS devices) formed in silicon layers (hereinafter suitably called SOI) on a buried oxide film has a Junction capacitance smaller than that of a normal CMOS device (bulk/CMOS device) formed in a well region and operates at high speed and with low power consumption. The SOI/CMOS devices are classified into two from the viewpoint of operating modes. Namely, they are classified into a perfect depletion type mode and a partial depletion type mode to be described later.
FIG. 10 is a cross-sectional view showing an NMOS transistor activated in a conventional perfect depletion type mode. In FIG. 10, reference numeral 101, reference numeral 102, reference numeral 103, reference numeral 104, reference numeral 105, reference numeral 106, reference numeral 107, reference numeral 108 and reference numeral 109 indicate a silicon substrate, a buried oxide film, a silicon layer, an oxide film, a gate oxide film, a gate electrode, a gate terminal, a source terminal and a drain terminal, respectively.
A voltage greater than or equal to a threshold voltage of the NMOS transistor is applied to the gate terminal 107. The transistor exhibits an ON state. In this condition, a channel region 110 for the NMOS transistor is formed below the gate electrode 106. A region (body region) located therebelow is perfectly depleted so as to form a depletion layer 111. A device activated in a state in which the body region is fully being depleted under the circumstances of the transistor being held ON in this way, is called perfect depletion type device.
FIG. 11 is a cross-sectional view showing a partial depletion type device. In FIG. 11, reference numeral 112 indicates a P+ body region. A voltage greater than or equal to a threshold voltage of an NMOS transistor is applied to a gate terminal 107. The transistor exhibits an ON state. Even if-the transistor is in the ON state, the P+ body region 112 exists in a portion below a depletion layer 111. Such a device is called partial depletion type device.
The operation will be next described.
If a comparison is performed between the two, then the perfect depletion type device has an S factor smaller than that of the partial depletion type device. Accordingly, a leakage current is small in the perfect depletion type device.
Owing to control on the potential of the P+ body region 112, the partial depletion type device can be reduced in threshold voltage in the ON state and activated at high speed.
Further, owing to the fixing of the potential of the body region, the partial depletion type device can improve a transistor withstand voltage as compared with the perfect depletion type device.
FIG. 12 is a view typically showing the symbol of an NMOS transistor. In FIG. 12, reference numeral 113 indicates a body terminal.
The operation of the NMOS transistor will next be described.
If the body terminal 113 of the NMOS transistor is used with being connected to a gate terminal 107, then a current that flows when the transistor is turned ON, increases so that a logic circuit is activated at high speed.
The body terminal 113 is normally used with being connected to a source terminal 108 of the transistor. If a voltage greater than or equal to the threshold voltage is applied between the source terminal 108 and the gate terminal 107, then the transistor is turned ON so that a current flows between a drain terminal 109 and the source terminal 108.
FIG. 13 is a graph showing the relationship between a voltage (Vds) applied between source/drain terminals and a current (Ids) that flows between the source/drain terminals. Referring to FIG. 13, each broken line indicates a current (Ids) flowing between the source/drain terminals when the voltage above the threshold voltage is applied between the source/gate terminals of the NMOS transistor. A large current flows as the voltage applied between the source/gate terminals increases.
Further, each solid line indicates a current (Ids) that flows between the source/drain terminals when the gate terminal is electrically connected to the body terminal. A very large current flows as compared with the case where the body terminal is electrically connected to the source terminal.
The MOS transistor circuit is logically operated by charging or discharging its output capacity through the current. Thus, the circuit using the transistor in which the body terminal is electrically connected to the source terminal, produces a large current between the source/drain terminals and is activated at high speed as compared with the normal circuit. The current that flows in the transistor wherein the body terminal is electrically connected to the gate terminal, increases because a back-gate bias effect is reduced and the threshold voltage of the transistor is lowered.
Since the back-gate bias effect is reduced as the voltage at the body terminal becomes greater than that at the source terminal as is already known, the threshold voltage of the NMOS transistor becomes low. Since the back-gate bias effect is reduced as the voltage at the body terminal becomes lower than that at the source terminal, the threshold voltage of the PMOS transistor becomes low.
These phenomena normally noticeably occur in the partial depletion type device whose body region is not perfectly depleted and do not appear in the perfect depletion type device whose body region is perfectly depleted.
Further, a resistive element is often used in a semiconductor circuit. The resistive element is formed by a diffused region (diffused resistance) formed in a bulk well region. The resistive element is realized by adding a process for forming the resistance of polysilicon (polysilicon resistance) set to a desired resistance value to the general process step.
The diffused resistance can be implemented without a change in normal process step. However, a depletion layer capacitance developed between the well and the diffused region is large and hence a large loss is produced when the diffused resistance operates at a high frequency.
On the other hand, the polysilicon resistance can be reduced in parasitic capacitance and used even in a high frequency region. Since, however, the number of process steps increases, this will result in an increase in chip cost.
Incidentally, JP-A-6/291265 discloses, for example, a CMOS integrated circuit wherein an NMOS transistor is formed in a thick silicon layer portion on a silicon oxide film and a PMOS transistor is formed in a thin silicon layer portion. However, each of the formed devices is different in type from that obtained by the invention of the present application.